My current research focuses on the design of the highest performance uniprocessors of a current generation. Currently we are investigating the architecture of a circa 2000 processor. With plenty of transistors available on a chip, the challenge is to use these resources to get the highest possible performance when executing a sequential program. A target that we have set for ourselves is to sustain the execution of over 10 instructions per cycle, for ordinary non-numeric application programs.
My research group is investigating several issues that need to be resolved before our goals can be achieved. We are studying and characterizing the nature of instruction-level parallelism in non-numeric application programs in order to understand the available parallelism and how it could be exploited. The bulk of my group's research effort is expended in continuing the development of the Multiscalar processing model, a novel paradigm for exploiting ILP. Currently we are developing the Multiscalar compiler, and carrying out detailed simulation studies to assess the potential of the Multiscalar concept.