Much of my work is performed using facilities of the VLSI digital system laboratory. The laboratory houses a number of workstations and PCs. I am investigating techniques to make the test generation and fault simulation processes efficient for both combinational and sequential circuits. In the area of built-in self-test, I am interested in both logic BIST as well as BIST for memory and other regular structures. My general research interests are test generation and testable and reliable design of digital systems. In my research I make extensive use of VLSI CAD and analysis tools. The research involves modeling of faults, designing digital circuits, test generation, design modification for enhancing testability, built-in self-testing designs, and test scheduling to optimize the test time under various constraints.