Kewal K. Saluja

Professor

4611 Engineering hall
1415 Engineering Drive
Madison, WI 53706

Ph: (608) 262-6490
saluja@engr.wisc.edu

Primary Affiliation:
Electrical and Computer Engineering

Additional Affiliations:
Computer Sciences,


Profile Summary

Much of my work is performed using facilities of the VLSI digital system laboratory. The laboratory houses a number of workstations and PCs. I am investigating techniques to make the test generation and fault simulation processes efficient for both combinational and sequential circuits. In the area of built-in self-test, I am interested in both logic BIST as well as BIST for memory and other regular structures. My general research interests are test generation and testable and reliable design of digital systems. In my research I make extensive use of VLSI CAD and analysis tools. The research involves modeling of faults, designing digital circuits, test generation, design modification for enhancing testability, built-in self-testing designs, and test scheduling to optimize the test time under various constraints.

Education

  • PhD 1973, University of Iowa

Research Interests

  • Design for testability
  • Built-in self-test
  • Computer architecture
  • VLSI design and testing
  • Fault-tolerant computing

Awards, Honors and Societies

  • Fellow of IEEE
  • Member of TBP, HKN, KHK

Publications

See my extended home page

Links

Courses

Fall 2014-2015

  • ECE 999 - Advanced Independent Study

  • ECE 990 - Research or Thesis
  • ECE 890 - Pre-Dissertator\'s Research
  • ECE 790 - Master\'s Research or Thesis
  • ECE 699 - Advanced Independent Study
  • ECE 553 - Testing and Testable Design of Digital Systems
  • Secondary Contact

    Room 4611
    Engineering Hall
    1415 Engineering Drive
    Madison, WI 53706

    Alt Ph: (608) 262-6490
    Alt Email: saluja@ece.wisc.edu

    Profile Summary

    Much of my work is performed using facilities of the VLSI digital system laboratory. The laboratory houses a number of workstations and PCs. I am investigating techniques to make the test generation and fault simulation processes efficient for both combinational and sequential circuits. In the area of built-in self-test, I am interested in both logic BIST as well as BIST for memory and other regular structures. My general research interests are test generation and testable and reliable design of digital systems. In my research I make extensive use of VLSI CAD and analysis tools. The research involves modeling of faults, designing digital circuits, test generation, design modification for enhancing testability, built-in self-testing designs, and test scheduling to optimize the test time under various constraints.


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